ARM Cortex_M4 Memory Design and Booting Sequence

Lets investigate the important parts to understand how the ARM Cortex-M4 works from the booting time.

1. Memory organization

The Cortex-M processors have 32-bit memory addressing and therefore have 4GB memory space.

RegionAddress RangeSizeFunction
Code0x00000000 – 0x1FFFFFFF512MB– Store program code, including default vector table.
SRAM0x20000000 – 0x3FFFFFFF512MB -Primarily for connecting SRAM, mostly on-chip SRAM
– Program code can be executed from this region
– The first 1MB of the SRAM region is bit addressable if the optional bit-band feature is included
Peripherals0x40000000 – 0x5FFFFFFF512MB– Use mostly for on-chip peripherals
– The first 1MB of the SRAM region is bit addressable if the optional bit-band feature is included
RAM0x60000000- 0x9FFFFFFF1GB– Contain two slots on 512MB memory space (total 1GB) for other RAM such as off chip memories
– Can be used for program code as well as data
Devices0xA0000000 – 0xDFFFFFFF1GB– Contain two slots on 512MB memory space (toal 1GB) for other peripheral
System 0xE0000000 – 0xFFFFFFFF512MB– Contain several part: Internal Private Peripheral Bus; External Private Peripheral Bus; Vendor-specific area

2. Code Region in detail

2.1. Vector table

The vector table holds the starting address of interrupts and system exception.

By default the vector table is located at the beginning of the memory space(address 0x00), and the vector address is arranged according to the exception number time four.

The vector table is normally defined in the startup codes provided by the microcontroller vendors.


The vector table used in startup code also contains the initial value of the main stack pointer (MSP).

One thing you need to note that the vector tables in the Cortex-M processors are different form the vector tables in traditional ARM processor. In traditional ARM processors, the vector tables contain instructions such as branch instruction to branch to appropriate handlers, whereas in Cortex-M, the vector table contains the starting addresses of exception handlers.

2.2. Physical remap

  • Boot mode configuration

Due to its fixed memory map, the code area starts from address 0x00000000 (accessed through the ICode/DCode buses) while the data area (SRAM) starts from address 0x20000000 (accessed through system bus).

The Cortex-M4 with FPU CPU always fetches the reset vector on the ICode bus, which implies to have the boot space available only in code area. STM32F4xE microcontrollers implement a special mechanism to boot from other memory.

  • Physical remap in STM32F411xE

Now look code CODE region area in detail you can see the memory mapping and boot mode remap in STM32F411xE

Based on the BOOT pin configuration, the corresponding memories can be remapped to Alias Area.

3. Booting sequence

Now we understand the basic concepts, lets see how they work in booting time.

  1. Power On Reset
  2. Execute boot loader in boot ROM
  3. Processor read BOOT pins to determine the booting mode. For example if BOOT0 is 0, Main Flash memory is mapped into Alias space from address 0x00000000
  4. Next processor fetch the first word from memory space. As the beginning of the memory space contains the vector table, and the first word in the vector table is the initial value for the Main Stack Pointer (MSP). Processor set up the MSP after that.
  5. Processor continues read the next word in vector table, now is reset vector, which contains the Reset_Handler() function address.
  6. Reset_Handler() function address is moved into Program Counter (PC) and processor starts running Reset_Handler()
  7. Inside Reset_Handler(), System_Init( ) function will be run first, follow is our application (main())

4. What can we do next?

Now we understand how the application can be run from booting time. I will show you how we can access System memory and build your own boot loader base on these concept.

See you soon.

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